/* SPDX-License-Identifier: GPL-2.0+ */

#ifndef __SUN50IW10_REG_NCAT_H__
#define __SUN50IW10_REG_NCAT_H__

#define SUNXI_SRAM_A1_BASE (0x00020000)
#define SUNXI_SRAM_A2_BASE (0x00100000)
#define SUNXI_SRAM_C_BASE (0x00024000)
#define SUNXI_CE_BASE (0x01904000)
#define SUNXI_SS_BASE SUNXI_CE_BASE

//CPUX
#define SUNXI_CPUXCFG_BASE (0x08100000)
#define SUNXI_CPU_SUBSYS_CTRL_BASE (0x08100000)

//sys ctrl
#define SUNXI_SYSCRL_BASE (0x03000000)
#define SUNXI_CCM_BASE (0x03001000)
#define SUNXI_DMA_BASE (0x03002000)
#define SUNXI_MSGBOX_BASE (0x03003000)
#define SUNXI_SPINLOCK_BASE (0x03004000)
#define SUNXI_HSTMR_BASE (0x03005000)
#define SUNXI_SID_BASE (0x03006000)
#define SUNXI_SID_SRAM_BASE 0x03006200
#define SUNXI_SMC_BASE (0x04800000)
#define SUNXI_SPC_BASE (0x03008000)
#define SUNXI_TIMER_BASE (0x03009000)
#define SUNXI_WDOG_BASE (0x030090A0)
#define SUNXI_CNT64_BASE (0x03009C00)
#define SUNXI_PWM_BASE (0x0300A000)
#define SUNXI_PIO_BASE (0x0300B000)
#define SUNXI_PSI_BASE (0x0300C000)
#define SUNXI_DCU_BASE (0x03010000)
#define SUNXI_GIC_BASE (0x03020000)
#define SUNXI_IOMMU_BASE (0x030F0000)

//storage
#define SUNXI_DRAMCTL0_BASE (0x04002000)
#define SUNXI_NFC_BASE (0x04011000)
#define SUNXI_SMHC0_BASE (0x04020000)
#define SUNXI_SMHC1_BASE (0x04021000)
#define SUNXI_SMHC2_BASE (0x04022000)

#define SUNXI_UART0_BASE (0x05000000)
#define SUNXI_UART1_BASE (0x05000400)
#define SUNXI_UART2_BASE (0x05000800)
#define SUNXI_UART3_BASE (0x05000c00)
#define SUNXI_UART4_BASE (0x05001000)

#define SUNXI_TWI0_BASE (0x05002000)
#define SUNXI_TWI1_BASE (0x05002400)
#define SUNXI_TWI2_BASE (0x05002800)
#define SUNXI_SCR0_BASE (0x05005000)

#define SUNXI_SPI0_BASE (0x05010000)
#define SUNXI_SPI1_BASE (0x05011000)
#define SUNXI_GMAC_BASE (0x05020000)

#define SUNXI_GPADC_BASE (0x05070000)
#define SUNXI_LRADC_BASE (0x05070800)
#define SUNXI_KEYADC_BASE SUNXI_LRADC_BASE

#define SUNXI_USBOTG_BASE (0x05100000)
#define SUNXI_EHCI0_BASE (0x05310000)
#define SUNXI_EHCI1_BASE (0x05311000)

#define ARMV7_GIC_BASE (SUNXI_GIC_BASE + 0x1000)
#define ARMV7_CPUIF_BASE (SUNXI_GIC_BASE + 0x2000)

// cpus
#define SUNXI_RTC_BASE (0x07000000)
#define SUNXI_CPUS_CFG_BASE (0x07000400)
#define SUNXI_RCPUCFG_BASE (SUNXI_CPUS_CFG_BASE)
#define SUNXI_RPRCM_BASE (0x07010000)
#define SUNXI_RPWM_BASE (0x07020c00)
#define SUNXI_RPIO_BASE (0x07022000)
#define SUNXI_R_PIO_BASE (0x07022000)
#define SUNXI_RTWI_BASE (0x07081400)
#define SUNXI_RRSB_BASE (0x07083000)
#define SUNXI_RSB_BASE (0x07083000)
#define SUNXI_RTWI_BRG_REG (SUNXI_RPRCM_BASE + 0x019c)
#define SUNXI_RTWI0_RST_BIT (16)
#define SUNXI_RTWI0_GATING_BIT (0)

#define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100)

/* use for usb correct */
#define ANALOG_SYS_PWROFF_GATING_REG (SUNXI_RPRCM_BASE + 0x254)
#define VDD_SYS_PWROFF_GATING_REG ANALOG_SYS_PWROFF_GATING_REG
#define RES_CAL_CTRL_REG (SUNXI_SYSCRL_BASE + 0x160)
#define VDD_ADDA_OFF_GATING (1)
#define CAL_ANA_EN (1)
#define CAL_EN (0)

#define RVBARADDR0_L (SUNXI_CPUXCFG_BASE + 0x40)
#define RVBARADDR0_H (SUNXI_CPUXCFG_BASE + 0x44)
#define SRAM_CONTRL_REG0 (SUNXI_SYSCRL_BASE + 0x0)
#define SRAM_CONTRL_REG1 (SUNXI_SYSCRL_BASE + 0x4)

#define GPIO_BIAS_MAX_LEN (32)
#define GPIO_BIAS_MAIN_NAME "gpio_bias"
#define GPIO_POW_MODE_REG (0x0340)
#define GPIO_POW_MODE_VAL_REG (0x0348)
#define GPIO_3_3V_MODE 0
#define GPIO_1_8V_MODE 1

/* sram layout*/
#define CONFIG_SYS_SRAM_BASE (0x20000)
#define CONFIG_SYS_SRAM_SIZE (0x4000)
#define CONFIG_SYS_SRAMA2_BASE (0x100000)
#define CONFIG_SYS_SRAMA2_SIZE (0x14000)
#define CONFIG_SYS_SRAMC_BASE (0x24000)
#define CONFIG_SYS_SRAMC_SIZE (0x21000)

/* scp mem layout */
#define SCP_DRAM_SIZE (0x0000) /* no cpus dram code on sun50iw10 */
#define SCP_DTS_SIZE (0x40000)
#define SCP_CODE_DRAM_OFFSET (0x14000)
#define SCP_SRAM_BASE (CONFIG_SYS_SRAMA2_BASE)
#define SCP_SRAM_SIZE (CONFIG_SYS_SRAMA2_SIZE)
#define HEADER_OFFSET (0x4000)

#endif// __SUN50IW10_REG_NCAT_H__
